Marvell launches Teralynx T100 switch chip for AI clusters

Marvell has introduced the Teralynx T100 switch chip for AI and cloud data centres, describing it as the first 102.4 Tbps switch silicon product aimed specifically at those workloads.

The product targets a growing infrastructure bottleneck as large AI systems demand more bandwidth and drive up rack-level power use. The chip is designed to cut latency and power consumption by removing older switch elements built for conventional enterprise and cloud networking.

According to Marvell, the T100 consumes under 1000W at typical power and uses up to 25% less power than rival products. That matters as GPU- and XPU-based systems approach 120KW per rack, with networking hardware accounting for about 15% to 25% of total rack power, based on SemiAnalysis data cited by the company.

Marvell is pitching the chip to operators building large AI clusters, where network design can affect how efficiently expensive accelerators are used. Lower network power draw could also allow more accelerators to be installed within existing power limits, reducing the need for additional electrical infrastructure.

AI focus

The Teralynx T100 is a monolithic 102.4 Tbps device built on a 3nm process. Marvell says this approach enables flatter network fabrics with fewer tiers and optical links, which could reduce latency and simplify the architecture of large AI deployments.

For scale-out systems, the chip supports up to a 512-port radix, which Marvell says allows operators to consolidate network tiers across clusters with tens of thousands of accelerators.

It is also aimed at scale-up designs. The switch has a programmable pipeline that supports multiple interconnect standards and newer scale-up protocols, including Ethernet Scale-Up Networking, as well as Ultra Ethernet Consortium requirements.

Deployment options include ball grid array, co-packaged copper, and co-packaged optics versions. The switch also includes telemetry, congestion control tuned for AI traffic, and traffic management functions for complex data centre networks.

The launch extends the Teralynx family, which spans products from 12.8 Tbps to 102.4 Tbps. The broader range also supports the Open Compute Project's Switch Abstraction Interface and the SONiC network operating system.

Rishi Chugh, Vice President and General Manager of the Data Centre Switch Business Unit at Marvell, outlined the company's position on AI network design. "As AI workloads evolve and scale exponentially, hyperscalers require network architectures that optimize latency, power and scalability simultaneously," Chugh said. "The Teralynx T100 was purpose-built for AI-designed without the legacy baggage that inflates power, and engineered to deliver the deterministic performance and efficiency required to scale next-generation data center infrastructure."

Market pressure

The announcement comes as chip and networking suppliers compete to provide the fabric linking ever larger numbers of AI accelerators inside training and inference clusters. As those installations grow, network switching is becoming a more prominent factor in both performance and operating cost.

Analyst Alan Weckel said those pressures are increasing the importance of network architecture choices for hyperscale operators. "As hyperscalers expand AI clusters to tens of thousands of accelerators, data center infrastructure becomes a defining factor in network efficiency and performance," Weckel said. "The Teralynx T100 architecture delivers significant advantages in latency, power efficiency, radix scalability and overall TCO-advantages that stem directly from its purpose-built AI design approach and are required for the continued scaling of data center infrastructure."

Marvell said the Teralynx T100 will begin sampling to customers this quarter.